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Yeps, you are right regarding the learning. I'm gonna create new forum post soon because I still can't get the ST testbench to work as it should. Hopefully a new post with a more appropriate title will get me some feedback from other members.

Hmmm.. just forget my previous message concerning $fread. I managed to get it working by adding a "rb" instead of "r" in $fopen. Dow!! I feel so stupid :)

Thanks for your continuous support Dave. I don't think this problem is related to ASE, because I have just installed the full edition (I didn't even know we had this license!) and I still face the same problem. The error is happening with the $fread command. For example, in the following line, read_index stays at 57671 when I look at the waveform window. It's expected to be NUMBER_OF_PIXEL_VALUES-1 instead.

 read_index = $fread(storage_values, fileInput, 0, `NUMBER_OF_PIXEL_VALUES-1); 

logic  val;
for (int i = 0; i < `NUMBER_OF_PIXEL_VALUES; i++)
begin
    @(posedge clk);
    val = storage_values;
end

Cheers Dave. I am doing the interactive testbench for now but I am having problems with reading the input data file. I have an array of size 153600 bytes that I save as follows in matlab:

fid = fopen('image_binval.bin', 'w');
fwrite(fid, data_image_1d,'uint8');
 

`define NUMBER_OF_PIXEL_VALUES 153600 
`timescale 1ns / 1ps
 
module sopc_system_tb();
  import verbosity_pkg::*;
 
  // 50MHz clock period
  localparam time CLK50_PERIOD = (1.0e9/50.0e6)*1ns;
 
  // Clock and reset
  logic clk;
  logic rstN;
 
  // Avalon ST
  typedef logic  AvalonSTData_t;
 
  reg   storage_values ; //153600 values for 640x240 image
 
  integer fileInput, r;
 
 
  //the ST transaction is defined using SystemVerilog structure data type
   typedef struct 
  {    int               idles;  //idle is not part of Avalon ST signal, it is used in BFM only
       bit               startofpacket;
       bit               endofpacket;
       AvalonSTData_t    data;
   } transaction_struct;
 
  transaction_struct src_transaction, snk_transaction; 
  int i, j;
  // 50MHz system clock
 initial
  clk = 1'b0;
 always
 # (CLK50_PERIOD/2) clk <= ~clk;
 
  // SOPC system -Set up the Dut
  sopc_system 
  dut
    (
      .clk_0   (clk),
      .reset_n (rstN)
    );
 
 
  // Stimulus
 // ------------------------------------------------------------
 
  initial
  begin
      // Initialize input and output text files
      fileInput  = $fopen("image_binval.bin", "r");
      r = $fread(storage_values, fileInput, 0, `NUMBER_OF_PIXEL_VALUES-1); 
 
      // Initialize the BFM
      // ------------------------------------------------------------
     set_verbosity(`VERBOSITY);
    `SRC.init();
    `SNK.init();
 
      rstN = 0;
     # 50ns rstN <= 1; 
 
      // --------------------------------------------------------
      $display("Simulation Start");
      // --------------------------------------------------------
 
       for (i = 0; i < `NUMBER_OF_PIXEL_VALUES; i++)
         begin 
          @(posedge clk);
          src_transaction.idles          = 0;       
          src_transaction.data           = storage_values;
 
          if (i == 0)   
              src_transaction.startofpacket  = 1;
          else
              src_transaction.startofpacket  = 0;
 
          if (i == `NUMBER_OF_PIXEL_VALUES-1)
              src_transaction.endofpacket    = 1;
          else
              src_transaction.endofpacket    = 0;
 
       end 
   end
 
 
endmodule
 
 
 

Many thanks again Dave. The timescale line fixed it. Yes you are right I have done only basic coding so far, nothing real world. One day perhaps... if I manage to survive all the FPGA learning. It's just that I've started learning about hardware programming around 4 months ago, but I feel that I spend most of my time learning how to use tools rather than actually doing anything productive. First it was Quartus, then SOPC, then NIOS SBT, now ModelSim.... But I guess it's the way to learn step by step.