dmx-512 vhdl/verilog code

800 I/O pins is a lot. I assume you created 100 output ports with 8-bit vectors? As I said I think it would be more practical to have two ports instead, one with the channel number and another one with the value.

The pin assingnment warning means exactly what it says. You forgot to assign pin numbers to your signals. You can do that on the pin planner, but I doubt you'll be able to fit all of them on your FPGA.

For the evaluation mode warning, you either need to install a license or use the web edition of Quartus

For the last 3 warnings it's probably a problem in your code.