dmx-512 vhdl/verilog code

i have written the code for 100 channels also but iam getting some warnings like below.,

Warning: No exact pin location assignment(s) for 813 pins of 813 total pins

Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details

Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.

Warning: Found 802 output pins without output pin load capacitance assignment

Warning: Can't generate programming files because you are currently using the Quartus II software in Evaluation Mode

Warning: Found pins functioning as undefined clocks and/or memory enables

Info: Assuming node "SysClk" is an undefined clock

Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew

Info: Detected ripple clock "RxUnit:RxDev|Start" as buffer

Warning: Circuit may not operate. Detected 38 non-operational path(s) clocked by clock "SysClk" with clock skew larger than data delay. See Compilation Report for details.