DMA problems with Stratix III 7.2 SP3

Hi,

I am experiencing problems not unlike those reported here:

http://www.altera.com/support/kdb/solutions/rd02192004_6389.html (http://www.altera.com/support/kdb/solutions/rd02192004_6389.html)

This was reported as fixed in V4.0.

I switched to using registers for the fifo and it has made no difference to the problem.

Basically, I see holes in the write data of varying sizes (I have pre-initialised the buffer before the dma so I know that it isn't being written to).

A test program seems to show that the problem varies according to DMA length and/or the destination address. I'm not sure which is more critical without doing lots of time consuming experimentation.

I'm using 32 bit only transfers between a LAN controller and SRAM. The DMA Controller is configured only for 32 bit transfers.

Memory test on the SRAM works fine as does reading the LAN controller.

Our design works OK without DMA so the system appears to be good.

All device timing is good (i.e.TimeQuest analysis results).

Any ideas ?

Regards,

D.