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Altera_Forum's avatar
Altera_Forum
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8 years ago

DMA Flow Control - Memory to Avalon MM Peripherals

Hello, Still rather new to FPGA design, and I had a question about implementing a DMA controller. If a DMA transfer is coordinated from a incrementing memory location to a simple MM-Slave...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Thanks for your response. I had no idea that the Platform Designer handled DMA interconnection architecture. Is there some documentation that describes that mechanism? That would have been incredibly helpful earlier on. Are there other automatic functionalities implied that I should be aware of moving forward?

Anyway, I'll give this a shot and see how it works out. Thanks again!