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Altera_Forum
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7 years ago

DMA Flow Control - Memory to Avalon MM Peripherals

Hello, Still rather new to FPGA design, and I had a question about implementing a DMA controller. If a DMA transfer is coordinated from a incrementing memory location to a simple MM-Slave...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

You can implement a FIFO yourself (add it as a component and parameterize it) or rely on the Qsys (Platform Designer) interconnect to do this for you. You'll have more control if you add the FIFO yourself.