DMA controller memory verification failed

Try a FIFO depth that is at least 4x the burst size. I don't know of any issue with the DMA that require it but with all the DMAs I designed that seems to be the minimum buffer depth you would want when bursting is involved for efficiency reasons. I also seem to recall some sort of weird issue where the transfer length had to be a multiple of the burst size, if that is still the case perhaps you are running into that issue.

The problem with using large burst sizes is you starve all other masters in your system from accessing the same memory. If you need that sort of functionality I recommend increasing the arbitration share (assuming you are using Qsys, in SOPC Builder arbitration share is ignored for bursting masters). The other problem is that most DMAs wait until there is enough data buffered to post a burst, so by increasing the burst size you can actually have a negative effect on your throughput since the write master will have to wait for more data to be read. Most memory controllers use burst lengths of 1, 2, or 4 on the slave side. So cranking the burst count up even higher than what the memory controller uses most of the time just results in additional hardware to adapt the large burst into smaller ones and no real gains in throughput.