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Altera_Forum's avatar
Altera_Forum
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15 years ago

division 2 integer value and output to the output reg

Hi, Is it can not direct using the division '/' in verilog?.. I notice that the result of division between two integers number and stored in the out reg gives red color words shown in Signal Ta...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Is it ALTFP_DIV?

I key in the floating pointing point format as Single precision (32 bits). However, the "how wide should the 'dataa' input and 'datab' input, and 'result' buses be" not allow me to key in 11 bits.

I try to use this 32 bits input and output module. When I run the signal tap that time, i saw the dividend and divisor is changing at the way i want. However, the result is fix at one value, not depending on the dividend and the divisor... Is there anything wrong with my module?..