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Altera_Forum's avatar
Altera_Forum
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15 years ago

division 2 integer value and output to the output reg

Hi, Is it can not direct using the division '/' in verilog?.. I notice that the result of division between two integers number and stored in the out reg gives red color words shown in Signal Ta...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hi,

I have found my mistake..

By the way, i trying to use the Altera megawizard to perform that division.

However, I notice the minimum bit allowed is 32 bit. If i only wan 11 bit for the divisor, dividend, and the result?..