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Altera_Forum
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13 years ago

divide by two operation in vhdl

Hai, I have write vhdl code for divide by two operation. Below is the short code: SRL16_a:process(CLK) begin -- SRL16 if CLK'event and CLK='1' then ...
Altera_Forum's avatar
Altera_Forum
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13 years ago

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Then, bp: -50/2=-25. And so on. Please correct me.

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-25 would be 0x1e7. Due to logic shift right, you get 0x0e7 instead, or 231.

For arithmetic shift, write 

bp <= add_temp(8) & add_temp(8 downto 1);