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Altera_Forum's avatar
Altera_Forum
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13 years ago

divide by two operation in vhdl

Hai, I have write vhdl code for divide by two operation. Below is the short code: SRL16_a:process(CLK) begin -- SRL16 if CLK'event and CLK='1' then ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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Hi , Your simulation shows that a1 dosent become valid for 08 clock cycles . If you can send me the complete VHDL files plus test bench i can take out some bugs . Regards ,

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Hai FPGA_guru011,

I will send to your e-mail. Hope you can helps. Thanks in advance