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Altera_Forum
Honored Contributor
Honored Contributordivide by two operation in vhdl
Hai, I have write vhdl code for divide by two operation. Below is the short code:
SRL16_a:process(CLK) begin -- SRL16
if CLK'event and CLK='1' then
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Altera_ForumHonored Contributor
Honored ContributorAccording to my manual calculation, the bp values are as expectable. You are doing a logical shift right, probably you want an arithmetical shift with sign extension?
