Honored Contributor
Honored ContributorIf you have a data cache on the CPU it's possible that the start and/or destination block are cached, and therefore the CPU reads and writes data from it's cache rather than the SDRAM. You have several ways around this:[list]
[*]Disable the data cache, or use the Nios II/e core [*]Do a cache flush on the source block before the dma transfer, and a cache invalidate on the destination block after [*]Bypass the cache when accessing the source and destination block, either though the IORD/IOWR macros, or by modifying the pointers with alt_remap_uncached()[/list]
