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Altera_Forum
Honored Contributor
Honored ContributorDesign Size and the timing accuracy
Dear Sir, I've met one problem. It is about the design size and timing accuracy. If I have a design which used up the FPGA 95% or above LEs, is it going to have some I/Os having worse tim...
Altera_ForumHonored Contributor
Honored ContributorDear GPK,
My design has been simplified to fit the FPGA. To post the original design, it takes time. I'll try to review my code, and then post it after. Thank you! Peter
