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Altera_Forum
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15 years ago

Design Size and the timing accuracy

Dear Sir, I've met one problem. It is about the design size and timing accuracy. If I have a design which used up the FPGA 95% or above LEs, is it going to have some I/Os having worse tim...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Dear GPK,

Thanks for your comment. I believe SDC is important for the timing constraints. However, is it possible that the requirements of my design

are over that FPGA could provide in timing, especially while the available

LEs are less.

Regards,

Peter Chang