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Altera_Forum
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18 years ago

Design begining phase..

Hi Friends... Here in this forum we had been talking a lot about timing, multicycle path etc etc..bla bla bla..... My doubt is, before we begin any design say 50 MHz, or 60 MHz or an...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Hi.

FPGA data sheet tells only the max operating freq of that device.

Suppose i need to implement a protocol running at 100 MHz. How can i expect that my design design will run at 100 MHz before coding that in HDL.

If my design spec cannot be met, there is no reason to say that it will run if the FPGA MAX freq is greater than design freq. What will be the case when i am going for an ASIC.

Regards

freak