derived clock versus clock enable

Brad,

Thanks for the advice. If I understand correctly, I need to have a clock setting entered for the 150 MHz clock. Then when I create a related clock setting for the 8.3 but do not enter an explicit offset or phase, Quartus will calculate the offset for me based on the timing of the counter used to generate the 8.3 and use that in timing analysis.

But in my design, the 150 MHz. is not an independent clock. It is being generated using a 6x output of a PLL driven by an independent 25 MHz. clock. So there isn't a clock setting for the 150; rather its timing is being calculated by Quartus based on the settings of the wizard-generated PLL megafunction. What then do I use as the base for the related 8.3 clock setting? I can't relate it to the 25 or I'll be missing the information derived from the PLL.

Bruce