Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Deos the plls of a fpga exactly same?

Hi, I have questions about pll. 1. If I use one clock source(27MHz) driving two plls in one fpga, and the parameter of plls is the same(generate 135MHz, but phase is same or different), Can ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Thanks Rysc. Very interesting post and design, as usual.

Unfortunately it's useless in my case. I need to use the dedicated PLL output pins. That's the reason I wanted to use two different PLLs in my case. Otherwise, I could simply use a single PLL. I guess I would need to use a single PLL and compensate the delay and jitter manually.