1 ReplyReplies sorted by Most LikedAnonymous6 years agoRead this: https://forums.intel.com/s/feed/0D50P00004ddfWDSAYDoc
Recent DiscussionsCyclone V SoC 5CSXC6 Series GXB Utilization and LimitationsMac internal loopback F-Tile, Quartus 25.2Cyclone 10 LP Device Pin MatchCyclone 10 GX development board collateralsGPIO default state before FPGA configuration (weak pull-up vs. pull-down)Solved
Occasional ContributorOccasional ContributorOccasional Contributor
