Honored ContributorWhat can I use in Quartus (Megawizard, options, ... ?) or Synplify_pro (RTL code) to delay my clock from a certain amount of time/degrees (around 2 ns) without using a PLL. The clock is coming at an input pin of the FPGA.
Honored ContributorWhat device are you targeting? Depending on the family, you might have some architectural features that could be used to give you the delay.
Honored ContributorThese ones are tough to answer simply because no matter how you delay a path in an FPGA, PVT variations will affect that delay. I used LCELLs in some of my CPLD designs to solve timing issues. It’s definitely not a good design practice to use LCELLs going in to a design. If you try to use routing to delay a signal, you’re still subject to PVT changes. The IOE has programmable delays you can use, but you need to make sure they are available for clock input pins. You can check in Quartus II if the dedicated clock pins have these delays.
Compile a simple project with at least 2 inputs, one on a standard I/O, the other on a clock pin. Look at each of the pins in the resource property editor. If you have 8 programmable delay settings for each one, that may be enough to delay your clock signal. I quickly did this with a dummy test design and if you click on the Clk pin assignment in the Assignment Editor -> Locate in Resource Property Editor You will see a properties box for the Clk pin. There are a couple of attributes here that you can use 1) Input pin to Input Register Delay -> 8 settings 2) Output Pin Delay -> 2 settings If this doesnt work then the LCELL may be the only option. There is no precise way of delaying the signal. The best way is to use PLLs for precise clock management, and even that has some degree of inaccuracy.
