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Altera_Forum's avatar
Altera_Forum
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15 years ago

Debugging interface issue on FPGA

Hi, I have a data processing module that takes only clock and reset as input and generate an expected sequence of data. When this design is tested in stand-alone mode, it works fine. But when i...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I have DDS for generating constant data. This data passes through different blocks, where it is modified in certain format. Once I resolve this issue, I will be replacing DDS with streaming data.

I have constrained the design and the small system works fine on hardware. When the small system is tried at different location, it worked fine on hardware too. Synthesizing large system with constraints does not report any violations. Since the large system is too big and has lot of latency, simulation is not an option.

Thanks for all the support.