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Altera_Forum's avatar
Altera_Forum
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15 years ago

Debugging interface issue on FPGA

Hi, I have a data processing module that takes only clock and reset as input and generate an expected sequence of data. When this design is tested in stand-alone mode, it works fine. But when i...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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I made sure that my module takes only clock and reset as input when integrated in bigger system to isolated data dependency problem.

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So where does the data come from? Something with only clock and reset must have a data source internally, so what is it?

Cheers,

Dave