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Altera_Forum
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14 years ago

Debugging interface issue on FPGA

Hi, I have a data processing module that takes only clock and reset as input and generate an expected sequence of data. When this design is tested in stand-alone mode, it works fine. But when i...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I was curious to know if any of the users faced a problem with Quartus where their design works fine in stand-alone mode and when integrated in a bigger system it fails. Assuming that the design has no problems and all the reports are clean.

Thanks