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Altera_Forum
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15 years ago

Debugging interface issue on FPGA

Hi, I have a data processing module that takes only clock and reset as input and generate an expected sequence of data. When this design is tested in stand-alone mode, it works fine. But when i...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

The data generated is sent off the chip to other device.

The data is passed through a DAC and observed on oscilloscope. In stand-alone mode, the output on oscilloscope is repetitive with a fixed pattern. When integrated in bigger system, the output is still repetitive but the pattern is wrong.

I made sure that my module takes only clock and reset as input when integrated in bigger system to isolated data dependency problem.

This integration of bigger system is done by a different team at different location and I do not have access to the board.

Thanks