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Altera_Forum
Honored Contributor
14 years agoaltrayeh...,
Can you describe little more on your DE4 board problem? Altera's example doesn't work well on DE4 board. PCIe pins connections are same, but the reference clock (free running) isn't. DE4 board has a clock selection dip switch, and you need to select to use 100MHz. Then in Altera's example, change input clock speed to 100MHz. This should give least x1 lane connection at Gen 1.