DE1SOC max. GPIO Header Frequency

There is no guarantee that you can get a 100 Mhz signal out of the FPGA if you don't follow the board layout guidelines. You can't brush this off or disaster awaits.

I've worked software on projects that had to be re-done because signals weren't handled correctly. The first design was done by a new grad with no experience. It was annoying because management wanted it fixed in software (impossible) or failing that VHDL (usually impossible). After several wasted months dithering around it was finally decided to give the board design to an engineer who did several high speed boards before and re-spin the board. Most of the problems were fixed the first day the revised board was powered on. The rest were fixed in the next week or so.