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Altera_Forum
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9 years ago

DDR3L interface query

Hi, As mentioned in the below schematic, we are using banks 7A and 8A of Cyclone V (5CEFA5F23C8) to interface to DDR3L memory device. For bank 7A, we are providing the voltage of DDR3L and we h...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

VREF is only needed for inputs. Since all of the signals in your bank 8A are address/control outputs (except for the diff clock input) I'm 99% sure you're fine to tie the VREF pin to GND. Read the handbook and pin connection guidelines to make sure.