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Altera_Forum
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13 years ago

DDR3 with HPC/Uniphy cores: what is the reason of the delays?

Hello. I am trying to work with DDR3 on Stratix V. I've made a variation of DDR3 controller (HPC/Uniphy) and try to write there an information. When I choose the "Half rate" for the logi...
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Altera_Forum
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13 years ago

Altera example design works with the same behaviour.

If the frequency of the DDR3 memory is 533MHz or below, refreshes are working as expected.

If the frequency is more than 533, unpredicted Read operation appears during the Refresh.