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Altera_Forum
Honored Contributor
Honored ContributorDDR3 with HPC/Uniphy cores: what is the reason of the delays?
Hello. I am trying to work with DDR3 on Stratix V. I've made a variation of DDR3 controller (HPC/Uniphy) and try to write there an information. When I choose the "Half rate" for the logi...
Altera_ForumHonored Contributor
Honored ContributorIt can be connected to the NIOS...
But during the write operations being discussed, it is constantly connected to the logic.
