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Altera_Forum
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13 years ago

DDR3 with HPC/Uniphy cores: what is the reason of the delays?

Hello. I am trying to work with DDR3 on Stratix V. I've made a variation of DDR3 controller (HPC/Uniphy) and try to write there an information. When I choose the "Half rate" for the logi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

What's the width of the memory chip(s) connected and the memory bus? If You're trying to write 16 bits data to 32bits chip running at half rate, then it's 64bits inside the controller, so You need to collect 4 packets to do such burst.