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matif's avatar
matif
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

DDR3 SDRAM Examle Design state machine

module Avalon_bus_RW_Test ( iCLK, iRST_n, iBUTTON, local_init_done, avl_waitrequest_n, avl_address, avl_readdatavalid, avl...
NurAida_A_Intel's avatar
NurAida_A_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Dear @matif​ ,

Is this coding (memory test module) obtained from Terasic board (please correct me if I'm wrong) ? Because I am not aware of this test module so far.

I would like to help but unfortunately I am not coding expert here. If this is the test module from Terasic, I suggest you to contact the Terasic vendor and address the query.

Please let me know your feedback or anything further I could help you. 😊

Thanks

Regards,

Aida