Honored ContributorHi all,
I have tried to find the "Maximum Theoretical Throughput" Data rate for DDR3 EMIF IP using 'Efficiency Monitor'. But, I wanted to know is there any other way, through which we can actually calculate this ? Thanks, Gokul
Honored ContributorThroughput strongly depends on your memory access pattern, so you can get exact result only by simulating. We got very good results with long bursts for reading and writing.
Honored ContributorHi Linas,
I was actually observing the 'Waitrequest' signal going high for long time. So, I though the 'waitrequest' plays a main role in determining the 'theoretical achievable maximum throughput'. I also observed that the 'waitrequest' is differing for each writes. Is there any standard measurement to measure this. so, that we can confirm the maximum range the EMIF IP will be working without any issues given that the data is coming at almost equal to DDR Clock. Also note that, we are using burst mode with burst count as 8. Thanks, GokulHonored ContributorWhat about access address? Are you accessing DDR3 continuously? We simulated write and read cycles of few HD video frames to get understanding about throughput. It took days on an elder Dell notebook with i5 CPU. Don't forget, that controller is also responsible for self-refresh operations.
Honored ContributorHi Lina,
I would like to know the controller's (Altera DDR3 EMIF IP) limitation here. We are accessing contagious address continuously for a fixed amount of data. Thanks, GokulHonored ContributorJust do the simulation and get the reliable data for your application. It is not that hard as it looks.
