Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

DDR3 calibration fail (Cyclone V + Micron DDR3 + Uniphy + NiOS)

Dear All, help me please in a trouble. I have a custom board with cyclonev (including Hard-IP DDR) and DDR3 (mt41j128m16jt-125). In quartus ii v14.1.0 (64bit) I created SoC (NIOSII + block ram ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Hi samuray,

we are using the same memory in a cyclone5 design. It works fine. Actually we have just one memory device. The hardware release before which had two devices with shared address/command bus and a 2 x 16 bit data bus also ran properly.

I think both designs use the same UniPhy settings. I will attach my current setting.

Jens