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Altera_Forum
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9 years ago

DDR3 calibration fail (Cyclone V + Micron DDR3 + Uniphy + NiOS)

Dear All, help me please in a trouble. I have a custom board with cyclonev (including Hard-IP DDR) and DDR3 (mt41j128m16jt-125). In quartus ii v14.1.0 (64bit) I created SoC (NIOSII + block ram ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Hi, when you generate the Qsys design, try choosing the create simulation model as "none"