Hi Julianus,
Altera only placed the DQ/DQS/DM parallel termination at the memory end as:
1) Their IP didn't at that time support the ODT features of the DDR2 memory.
2) They hadn't characterised the effectivess of the OCT FPGA features.
Hence now that the IP does directly support the DDR2 ODT feature, parallel termination on the DQ/DQS/DM pins is NOT usually required at the memory end of the line.
Note that DDR2 ODT does NOT act on the address/control signals, so its usually a good idea to continue to descrete terminate these signals at the memory end of the line.
As this is Cyclone II you are talking about, and hence the max possible rate is "only" 167MHz, often its not actually necessary to parallel terminate to VTT at the FPGA end of the line either, but you should simulate this first yourself for your actual implementation before you decide one way or the other on this point.
Altera has a useful application note on this very subject, which you should take a look at if your thinking about termination. Its written with respect to Stratix II, but as we are really talking about SSTL-18 and DDR2 termination it actully really applies to ALL devices. It can be found at:
http://www.altera.com/literature/an/an408.pdf They also supply the Hyperlynx test bed that they used for the simulations:
http://www.altera.com/literature/an/an408_example.zip Hope my answer helps you out.
Enjoy
Honored Contributor
