Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

DDR2 Memory Controller on Cyclone IV: Pin placement error with VREF

Hello Everybody, I'm working on a CycloneIV design with an DDR2 SDRAM controller. To find the correct pin placement for the PCB design, I'm verifying it with a stripped down project that so far...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

After some more searching in Quartus II, I found that I needed to modify the "ddr2_pin_assignments.tcl" to fit my pin names in the top VHDL.

Cheers,

Simon