DDR2 interface problem

Question

When I tried to fit my design into Cycleon II, I got an error message

Error: DQS I/O pin "ddr2_dqs[1]" does not feed a Clock Delay Control block

I use Altera's DDR2 controller, why does this happen? Do I need put a "altdqs" megafunction between the DQS output of the DDR2 Controller and the DQS pin on FPGA?

altera_forum · Answer

I've the same problem. Do you know the solution?

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DDR2 interface problem

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