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Altera_Forum's avatar
Altera_Forum
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13 years ago

DDR2 design compilation very long !

Hi, I'm currently trying to test a DDR2 (MT47H32M16 -25E) on a board but the compilation time is very very long... (more than 4 hours for a block diagram with only one PLL and a DDR2 SDRAM Con...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I think I found why it didn't worked. By deleting signal_tap block on the top design, the compilation take only 5 minutes.