DDR2_core is can't work

hello:

I have a question ,about the ddr2_core init。the DDR can not be worked

I use the EP3c40f484I7,and generate a DDR2_core ,so it should include the ddr2 init,but it not ,

when power turn on ,the pin of cas_n should be pulsing ,but it is high 。and the ras_n ,cs_n ,we_n(NOP) is same to it

another question ,when I use signaltop they(RAS_N/CAS_N/WE_N) display low ,but use oscilloscope(OSC) they are high. why ?

Oh in the signaltop the clock of FPGA to DDR2(MT47H32M16CC- 3) is low,but the oscilloscope is 192Mhz clock (it is right ,I set 125Mhz and 192Mhz).。I can't understand 。

I can be sure the DDR2 reset_n is low ,the 125Mhz is right .

how can I do ?

the project can run sucessfully at another board ,the FPGA is Ep3c120F780C7

THANK YOU

272049457 (http://wpa.qq.com/msgrd?v=1&uin=272049457&site=中国电子顶级开发网论坛&menu=yes)MSN:

272049457 (http://wpa.qq.com/msgrd?v=1&uin=272049457&site=中国电子顶级开发网论坛&menu=yes)MSN: