Forum Discussion

Honored Contributor

13 years ago

DDR SDRAM pin assign problem

Hi, I'm trying to have a pin-assignment of EP3C55U484C7 with DDR SDRAM. I read the pin information for the Cyclone III EP3C55 device. but after assignment, threre are errors during compilati...

Altera_Forum

Honored Contributor

13 years ago

Now, Compilation is finished successfully. DQs and DM were connected to DQ5B group when compilation was failed.

I got a successful compilation after I changed DQs and DM into DQ3B group.

But I can't understand the reason why. Anybody knows why?

Forum Discussion

DDR SDRAM pin assign problem

Recent Discussions

Agilex 5 FPGA EMIF: sharing LPDDR4 reference clock between Bank 3A and Bank 3B

FPGA firmware signing, agilex3

vertical side marking on MAX10 UBGA169 package?

About EPCQ-L device

Configuration using the MT25QU01GBBB8E12-0SIT