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Altera_Forum
Honored Contributor
Honored Contributorddr bi-directional with different input/output clocks
Greetings, I am wondering what the correct megafunctions/primitives are for implementing input/output dual-data-rate data lines for a DDR memory device. I'm on a Cyclone IV. Here are my require...
Altera_ForumHonored Contributor
Honored ContributorTurns out all I had to do was invert the DQS signal.
