Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributorddr bi-directional with different input/output clocks
Greetings, I am wondering what the correct megafunctions/primitives are for implementing input/output dual-data-rate data lines for a DDR memory device. I'm on a Cyclone IV. Here are my require...
Altera_ForumHonored Contributor
Honored ContributorOkay, that seems like the culprit. Unfortunately I don't control the inclock (DQS is driven from external device during reads), so I can't give it another clock. Are there any other options for making this scheme work? Sure someone has interfaced with a DDR memory controller?
