dct verilog

hi,

I downloaded the DCT verilog module from the altera website. (I cant post the link due forum limitations, but it's the first search result in google for "DCT verilog altera")

I ran a simulation using simple testbench that sends 0,1,2,...63 as the input parameters. The dct_out(output signal) never sends out any result and it always xxxxxx. From the initial basic understanding of the code, the reading the writing of local memory seems done incorrectly.

Also the original code has some compilation errors which is given below. Some of the reg needed to be converted to wires to compile. It didn't not seem to alter the functionality.

Error (10663): Verilog HDL Port Connection error at dct.v(88): output or inout port "result" must be connected to a structural net expression.

Is this IP tested and verified?

Thanks

regards

Shakith