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Honored Contributor
Honored ContributorDCFIFO turns into LIFO
Hello, I encountered a strange behaviour in one of my design in which I use a DCFIFO. The fifo is used to convert a 32 input to 8 bit output with rdclk different from wrclk. The configurat...
Altera_ForumHonored Contributor
Honored ContributorI assume you are using a recent Cyclone III or IV FPGA.
You said that you put the metastability protection to 3 stages. Did you enter the value '3' in the component instantiation? If so, you only have 1 FF sync stage as from Cyclone II and Stratix II onwards a value of '2' gets deducted. Altera always surprises us in mysterious ways :rolleyes:
