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Altera_Forum
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15 years ago

DC offset removal using FPGA?

I am new to interface FPGAs with DSP concepts. I have ADCs and then i have deserializers after them to parallelize the data. So should i apply the DC removal after the deserializer or before it? ...
Altera_Forum's avatar
Altera_Forum
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15 years ago

Hello researcher_123 (http://www.alteraforum.com/forum/member.php?u=51541):

Why don't you use histogram and get the DC value?

Hello Dave:

We used AC couple for our system, but there is still DC inside FPGA after ADC sampling without any signal feeding, why?

Thanks

Jerry