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Altera_Forum
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15 years ago

DC offset removal using FPGA?

I am new to interface FPGAs with DSP concepts. I have ADCs and then i have deserializers after them to parallelize the data. So should i apply the DC removal after the deserializer or before it? ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Filters do their filtering job in the frequency domain. Filters as such cannot selectively remove samples from time domain signal but you can either ignore initial stream as it is washed away or discard these samples through logic. Most receivers need time to lock and several msec of data are washed away before they make use of received data.