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Altera_Forum's avatar
Altera_Forum
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13 years ago

Data synchronization issue

Hi, I am facing an issue while synchronizing data between two clock domains. clka is at 200Mhz, coming in to the FPGA (phase not known) clkb is at 200Mhz 180 Phase shifted (generated fro...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

As I said, with a dcfifo with two or more stages, a false path exception is inserted and timing is simply not analyzed.

So, you won't get a slack report no mater what.

Try to reduce it to a single stage dcfifo and see what you get in timing analysis.