Honored Contributor
Honored ContributorI assume you are referring to this board:
http://www.altera.com/literature/manual/rm_data_conversion_hsmc.pdf I did not look for example code, but I am sure there are Altera application notes that could be reimplemented for this board. The first things I would do are; 1) ADC test * capture ADC samples using DDR I/O registers and then write data to FPGA RAM 2) DAC test * read data from FPGA RAM send it using DDR I/O to the DAC Test the dynamic range of the ADC using a sinusoid or noise source from an external generator with better than 14-bits. If you don't have something like that, then you can use the 14-bit DAC, but you won't be able to tell with the DAC is the limiting factor for the signal-to-noise or the ADC. Read the following for ADC test procedures: http://www.ovro.caltech.edu/~dwh/carma_board/digitizer_tests.pdf (http://www.ovro.caltech.edu/%7edwh/carma_board/digitizer_tests.pdf) and the following for some digital signal processing ideas http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-320paper_hawkins.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc-320paper_hawkins.pdf) Cheers, Dave
