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Altera_Forum
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15 years ago

cyclone4 memory controller

Hi I am trying to build a memory controller to interface two MT47H32M16BN DDR2 devices to a Cyclone4 GX30 FGG484 FPGA. I have got the project to compile successfully but when I run the fitter I ge...
Altera_Forum's avatar
Altera_Forum
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15 years ago

Use different output enable groups. Set DQ,DQS,ADDR pins to output enable group "1" or any different value... E.g. "123456" is also OK.