cyclone3 : maximum DDR input rate with LVDS

You're quite right: the logic will capture on both the rising and falling clock edge.

SDC are the Synopsis Design Constraints you have to provide so the Quartus Fitter, using the TimeQuest timing analyzer, can do a good job.

Once you have constrained and fitted the logic it will work for every production board. As we are still talking moderate speeds over here there is no need for special training and adjusting logic. Receiving data from the sensor is a one way point to point connection, so the sensors clock to output delays are well known. If the physical routed lengths of the channels are kept equal (to some extent, they may differ by a few mm) you do not need to take the board delay into account.

You do not need the high-speed inputs of the Cyclone IV, just use the normal LVDS channels of the devices (there may be a speed difference between the 'row' and the 'column' banks). The major advantage of Cyclone IV is mostly power consumption and of course for the GX-family the high-speed channels and the PCIe hard IP. Apart from that they seem to have an equal amount of resources as Cyclone III.

Simulating is always a good idea, you can use the QuartusII internal simulator ( that's what I do) or use the external Modelsim simulator. The Modelsim simulator needs some model of the sensor (to obtain from the vendor, or make yourself) whereas the waveforms used by the internal are easy to create, even down to picoseconds precision.

Once correctly simulated, it will also work on the board.